Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DYNAJUST: an efficient automatic routing technique optimizing delay conditions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance-driven Steiner tree algorithm for global routing
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SSTT: efficient local search for GSI global routing
Journal of Computer Science and Technology
TIGER: an efficient timing-driven global router for gate array and standard cell layout design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing optimization for multisource nets: characterization and optimal repeater insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Priority-based routing resource assignment considering crosstalk
Journal of Computer Science and Technology
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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A novel method, named critical-network-based (CNB), for timing optimization in global routing is presented in this paper. The essence of this method is different from that of the typical existing ones, named nets-based (NB) and critical-path-based (CPB). The main contribution of this paper is that the CNB delay reduction method is more efficient than the typical existing ones. This new method makes it possible to reduce the delay in an overall survey. Based on CNB, a timing optimization algorithm for global routing is implemented and tested on Microelectronics Center of North Carolina (MCNC) benchmarks in this paper. The experimental results are compared between this algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay efficiently.