Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Router system for printed wiring boards of very high-speed, very large-scale computers
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
A minicomputerized automatic layout system for two-layer printed wiring boards
DAC '77 Proceedings of the 14th Design Automation Conference
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
Basic concepts of timing-oriented design automation for high-performance mainframe computers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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A new routing technique DYNAJUST, Dynamic Wire Length Adjustment, is described. It accurately realizes specified wire lengths to fulfill delay conditions. The implementation, based on the combination of shortest path algorithms, is proposed to achieve a high completion ratio in a short processing time. The technique is useful in practical situations where high accuracy is required of many nets.