An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Integration, the VLSI Journal
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
| Hi-index | 0.03 |
This paper presents new results in the area of timing optimization for multisource nets. The augmented RC-diameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we characterize the multisource optimization problem in terms of operations on piece-wise linear functions. This characterization is then used to develop an algorithm for optimal repeater insertion: for a given multisource topology the algorithm efficiently identifies an optimal assignment of repeaters to prescribed insertion points under the “min cost timing feasible” problem formulation. The algorithm has been implemented and computational results demonstrate the viability of the approach