A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical repeater insertion method in high speed VLSI circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-Dominated VLSI Design
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A repeater optimization methodology for deep sub-micron, high-performance processors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing optimization for multisource nets: characterization and optimal repeater insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect synthesis without wire tapering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Constant impedance scaling paradigm for interconnect synthesis
Proceedings of the 2006 international workshop on System-level interconnect prediction
Constant Impedance Scaling Paradigm for Scaling LC transmission lines
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Impact of process parameters on circuit performance for the 32nm technology node
Microelectronic Engineering
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Exponentially tapered h-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the repeaters driving a line. The optimum repeater system uses uniform repeater insertion in order to achieve the minimum propagation delay. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum repeater system. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low-power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example repeater system.The Power-Delay-Area-Product (PDAP) criterion is introduced as an efficient technique to size the interconnect within a repeater system. A reduction in buffer area of 67% and interconnect area of 46% is achieved based on the PDAP.