Impact of process parameters on circuit performance for the 32nm technology node

  • Authors:

  • A. Farcy;M. Gallitre;V. Arnal;M. Sellier;L. Guibe;B. Blampey;C. Bermond;B. Fléchet;J. Torres

  • Affiliations:

  • STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France;STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France and LAHC Université de Savoie, Le Bourget du Lac, France;STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France;STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France;NXP Semiconductors, 860 rue Jean Monnet, 38926 Crolles Cedex, France;LAHC Université de Savoie, Le Bourget du Lac, France;LAHC Université de Savoie, Le Bourget du Lac, France;LAHC Université de Savoie, Le Bourget du Lac, France;STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2007

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Abstract

As IC dimensions scale down to the 32nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.