Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
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Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nano second region, increased cross talk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).