Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

Authors:
Raguraman Venkatesan;Jeffrey A. Davis;Keith A. Bowman;James D. Meindl
Affiliations:
Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA;Georgia Institute of Technology, Atlanta, GA
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

Minimum power CMOS ASIC macrocells are designed by minimizing the macrocell area using a new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures. The minimum macrocell area and power dissipation are projected for the 100, 70 and 50 nm technology generations and compared with a n-tier design without using repeaters. Repeater insertion and a novel interconnect geometry scaling technique decrease the power dissipation by 58-68% corresponding to a macrocell area reduction of 70-78% for the global clock frequency designs of these three technology generations.