Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preservingthe signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasingthe inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.