Buffered Steiner trees for difficult instances

Authors:
C. J. Alpert;Miloš Hrkić;J. Hu;A. B. Kahng;J. Lillis;B. Liu;S. T. Quay;S. S. Sapatnekar;A. J. Sullivan;P. Villarrubia
Affiliations:
IBM Corp., Austin, TX;University of Illinois at Chicago, EECS Dept., Chicago, IL;IBM Corp., Austin, TX;University of California at San Diego, CS Dept., San Diego, CA;University of Illinois at Chicago, EECS Dept., Chicago, IL;University of California at San Diego, CS Dept., San Diego, CA;IBM Corp., Austin, TX;University of Minnesota, ECE Dept.;IBM Corp., Austin, TX;IBM Corp., Austin, TX
Venue:
Proceedings of the 2001 international symposium on Physical design
Year:
2001

Citing 10
Cited 13

Performance-driven interconnect design based on distributed RC delay model

DAC '93 Proceedings of the 30th international Design Automation Conference
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Proceedings of the 1997 international symposium on Physical design
Buffer insertion with accurate gate and interconnect delay computation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Maze routing with buffer insertion and wiresizing

Proceedings of the 37th Annual Design Automation Conference
Simultaneous Routing and Buffer Insertion for High Performance Interconnect

GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Near-optimal critical sink routing tree constructions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Buffer insertion with adaptive blockage avoidance

Proceedings of the 2002 international symposium on Physical design
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages

Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis

Proceedings of the 39th annual Design Automation Conference
A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An efficient hierarchical timing-driven Steiner tree algorithm for global routing

Integration, the VLSI Journal
CNB: a critical-network-based timing optimization method for standard cell global routing

Journal of Computer Science and Technology
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Tradeoff routing resource, runtime and quality in buffered routing

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient generation of short and fast repeater tree topologies

Proceedings of the 2006 international symposium on Physical design
Integer Linear Programming Models for Global Routing

INFORMS Journal on Computing
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization

Proceedings of the 2009 international symposium on Physical design
A routing paradigm with novel resources estimation and routability models for x-architecture based physical design

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints

Proceedings of the 2014 on International symposium on physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Buffer insertion has become an increasingly critical optimization in high performance design. The problem of finding a delay-optimal buffered Steiner tree has been an active area of research, and excellent solutions exist for most instances. However, current approaches fail to adequately solve a particular class of real-world “difficult” instances which are characterized by a large number of sinks, variations in sink criticalities, and varying polarity requirements. We propose a new Steiner tree construction called C-Tree for these instance types. When combined with van Ginneken style buffer insertion, C-Tree achieves higher quality solutions with fewer resources compared to traditional approaches.