A new polynomial-time algorithm for linear programming
Combinatorica
Convergence of an annealing algorithm
Mathematical Programming: Series A and B
Experimental results for a linear program global router
Computers and Artificial Intelligence
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Attractor-repeller approach for global placement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
An exact algorithm for coupling-free routing
Proceedings of the 2001 international symposium on Physical design
Provably Good Global Routing of Integrated Circuits
SIAM Journal on Optimization
DAC '78 Proceedings of the 15th Design Automation Conference
Automated rip-up and reroute techniques
DAC '82 Proceedings of the 19th Design Automation Conference
A timing-constrained simultaneous global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On routing in VLSI design and communication networks
Discrete Applied Mathematics
Approximating the Generalized Capacitated Tree-Routing Problem
COCOON '08 Proceedings of the 14th annual international conference on Computing and Combinatorics
A multilevel congestion-based global router
VLSI Design
On routing in VLSI design and communication networks
ISAAC'05 Proceedings of the 16th international conference on Algorithms and Computation
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Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. These factors dictate that interconnections, i.e., wires, be made as short as possible. The wire-minimization problem is generally formulated as a sequence of discrete optimization subproblems that are known to be NP-hard. Hence, they can only be solved approximately using meta-heuristics. These methods are computationally expensive and the quality of the solution depends to a great extent on an appropriate choice of starting configuration and modeling techniques. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global routing heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. By adding information such as channel congestion and the number of pins in each route as well as the wire length, the quality of the solution is improved. In addition, the solutions of the large relaxed linear programming problems are skewed towards a zero-one solution, resulting in faster convergence. The developed LP models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, “near optimal wiring” is obtained in polynomial time without performing randomized rounding.