A fast and simple Steiner routing heuristic
Discrete Applied Mathematics - Special volume on VLSI
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Preferred direction Steiner trees
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Efficient minimum spanning tree construction without Delaunay triangulation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Maintaining Dynamic Minimum Spanning Trees: An Experimental Study
ALENEX '02 Revised Papers from the 4th International Workshop on Algorithm Engineering and Experiments
Approaching the 5/4-Approximation for Rectilinear Steiner Trees
ESA '94 Proceedings of the Second Annual European Symposium on Algorithms
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
A new heuristic for rectilinear Steiner trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
Wirelength reduction by using diagonal wire
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient octilinear Steiner tree construction based on spanning graphs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
The polygonal contraction heuristic for rectilinear Steiner tree construction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Circuit simulation based obstacle-aware Steiner routing
Proceedings of the 43rd annual Design Automation Conference
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
An efficient rectilinear Steiner tree algorithm with obstacles
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture
IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems
WSEAS Transactions on Circuits and Systems
A near linear time approximation scheme for Steiner tree among obstacles in the plane
Computational Geometry: Theory and Applications
Algorithm engineering: bridging the gap between algorithm theory and practice
Algorithm engineering: bridging the gap between algorithm theory and practice
Dealing with large hidden constants: engineering a planar steiner tree PTAS
Journal of Experimental Algorithmics (JEA)
Approximation of octilinear steiner trees constrained by hard and soft obstacles
SWAT'06 Proceedings of the 10th Scandinavian conference on Algorithm Theory
Hardness and approximation of octilinear steiner trees
ISAAC'05 Proceedings of the 16th international conference on Algorithms and Computation
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Power optimization for clock network with clock gate cloning and flip-flop merging
Proceedings of the 2014 on International symposium on physical design
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The rectilinear Steiner minimum tree (RSMT) problem, which asks for a minimum-length interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle nets with tens of thousands of terminals. In this paper we give a practical O (n log2 n) heuristic for computing near-optimal rectilinear Steiner trees based on a batched version of the greedy triple contraction algorithm of Zelikovsky [21]. Experiments conducted on both random and industry testcases show that our heuristic matches or exceeds the quality of best known RSMT heuristics, e.g., on random instances with more than 100 terminals our heuristic improves over the rectilinear minimum spanning tree by an average of 11%. Moreover, our heuristic has very well scaling runtime, e.g., it can route a 34k-terminals net extracted from a real design in less than 25 seconds compared to over 86 minutes needed by the O(n2) edge-based heuristic of Borah, Owens, and Irwin [3]. Since our heuristic is graph-based, it can be easily modified to handle practical considerations such as routing obstacles, preferred directions, via costs, and octilinear routing - indeed, experimental results show only a small factor increase in runtime when switching from rectilinear to octilinear routing.