Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Efficient Steiner tree construction based on spanning graphs
Proceedings of the 2003 international symposium on Physical design
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree
Proceedings of the 2008 international symposium on Physical design
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
High-performance obstacle-avoiding rectilinear steiner tree construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Proceedings of the 46th Annual Design Automation Conference
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection
Proceedings of the 2009 International Conference on Computer-Aided Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing terminals as input ports and Hanan nodes as output ports. We show that the faster an output reaches its peak, the higher the possibility for the correspondent Hanan node to be a Steiner point. Iteratively adding one or multiple selected Steiner points to build and improve Steiner trees leads to 1-cktSteiner and Blocked-cktSteiner (in short, B-cktSteiner) algorithms, respectively. When there are no routing obstacles, 1-cktSteiner obtains similar wirelength compared with the best existing algorithm FastSteiner. Both are less than 1% worse than the exact solution, but 1-cktSteiner is up to 11.3X faster than FastSteiner. Compared with the fastest existing heuristic FLUTE, B-cktSteiner has similar runtime but up to 1.9% shorter wirelength. Different from FastSteiner and FLUTE which are only applicable to non-obstacle cases, 1-cktSteiner and B-cktSteiner can be applied to routing with obstacles with minimal runtime increase. Compared with the best existing obstacle-avoiding algorithm An-OARSMan, 1-cktSteiner has similar runtime and reduces wirelength by 6.12%, and B-cktSteiner has an average speedup of 352X with a similar wirelength.