Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
Physical Planning Of On-Chip Interconnect Architectures
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Rotationally optimal spanning and Steiner trees in uniform orientation metrics
Computational Geometry: Theory and Applications
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Steiner trees for fixed orientation metrics
Journal of Global Optimization
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Flexibility of steiner trees in uniform orientation metrics
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The Y-architecture for on-chip interconnect is based on pervasiveuse of 0-, 120-, and 240-degree oriented semi-global and globalwiring. Its use of three uniform directions exploits on-chip routingresources more efficiently than traditional Manhattan wiring architecture.This paper gives in-depth analysis of deployment issues associatedwith the Y-architecture. Our contributions are as follows:(1) We analyze communication capability (throughput of meshes)for different interconnect architectures using a multi-commodityflow approach and a Rentian communication model. Throughput ofthe Y-architecture is largely improved compared to the Manhattanarchitecture, and is close to the throughput of the X-architecture.(2) We propose a symmetrical Y clock tree structure with bettertotal wire length compared to both H and X clock tree structures,and better path length compared to the H tree. (3) We discuss powerdistribution under the Y-architecture, and give analytical and SPICEsimulation results showing that the power network in Y-architecturecan achieve 8.5% less IR drop than an equally-resourced power networkin Manhattan architecture. (4) We propose the use of via tunnelsand banks of via tunnels as a technique for improving routabilityfor Manhattan and Y-architectures.