Flexibility of steiner trees in uniform orientation metrics

Authors:
Marcus Brazil;Pawel Winter;Martin Zachariasen
Affiliations:
ARC Special Research Centre for Ultra-Broadband Information Networks, Department of Electrical and Electronic Engineering, The University of Melbourne, Victoria, Australia;Department of Computer Science, University of Copenhagen, Copenhagen Ø, Denmark;Department of Computer Science, University of Copenhagen, Copenhagen Ø, Denmark
Venue:
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
Year:
2004

Citing 8
Cited 1

On some distance problems in fixed orientations

SIAM Journal on Computing
The X architecture: not your father's diagonal wiring

SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Minimum Networks in Uniform Orientation Metrics

SIAM Journal on Computing
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem

ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
Delay-related secondary objectives for rectilinear Steiner minimum trees

Discrete Applied Mathematics - The 1st cologne-twente workshop on graphs and combinatorial optimization (CTW 2001)
A new paradigm for general architecture routing

Proceedings of the 14th ACM Great Lakes symposium on VLSI
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Creating and exploiting flexibility in rectilinear Steiner trees

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A new paradigm for general architecture routing

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present some fundamental flexibility properties for minimum length networks (known as Steiner minimum trees) interconnecting a given set of points in an environment in which edge segments are restricted to λ uniformly oriented directions These networks are referred to as λ-SMTs They promise to play an increasingly important role in the future of optimal wire routing in VLSI physical design, particularly for the next generation of VLSI circuits In this paper we develop the concept of a flexibility polygon for a λ-SMT, which is a region representing the union of all (minimum length) λ-SMTs with the same topology on a given set of points We show that this polygon can be constructed, for a given point set and given topology, in linear time We discuss some of the future applications of this polygon, which can be thought of as a geometric representation of the amount of flexibility inherent in a given λ-SMT.