On some distance problems in fixed orientations
SIAM Journal on Computing
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Minimum Networks in Uniform Orientation Metrics
SIAM Journal on Computing
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Flexibility of steiner trees in uniform orientation metrics
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
A near linear time approximation scheme for Steiner tree among obstacles in the plane
Computational Geometry: Theory and Applications
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Approximation of octilinear steiner trees constrained by hard and soft obstacles
SWAT'06 Proceedings of the 10th Scandinavian conference on Algorithm Theory
Hardness and approximation of octilinear steiner trees
ISAAC'05 Proceedings of the 16th international conference on Algorithms and Computation
Flexibility of steiner trees in uniform orientation metrics
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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The interest in alternatives to traditional Manhattan routing has increased tremendously during recent years. The so-called Y- and X-architectures have been proposed as architectures of the future. Manhattan, Y- and X-architectures are special cases of a general architecture in which a fixed set of uniformly oriented directions is allowed. In this paper we present a new paradigm for routing in this general architecture. The routing algorithm is based on a concept of flexibility polygons for Steiner minimum trees --- a new way of describing the inherent flexibility of Steiner trees in uniform orientation metrics. Flexibility polygons characterize possible routing regions for the nets while keeping their netlength at a minimum. The proposed routing algorithm first routes nets that intersect highly congested areas of the chip --- as given by the flexibility polygons --- and then employs dynamic maze (liquid) routing. Experiments with industrial chips show great promise for this new routing paradigm.