On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 41st annual Design Automation Conference
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Y architecture for on-chip interconnect: analysis and methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Y architecture has recently received much attention due to its many potential advantages, such as substantially reduced wirelength, power consumption and significantly improved throughput. To fully utilize the virtues of Y architecture, several hexagon/triangle placement (HTP) algorithms suitable for the Y architecture were presented, however the wirelength optimization is not included in the algorithms. Wirelength estimation is fundamental to guide the wirelength optimization process in early design stages. In this paper, we present an accurate and efficient wirelength estimation technique called APWL-Y appropriate for the Y architecture, and especially for HTP floorplanner and placer. The average error of APWL-Y is 4.41% for 1.57 million nets from industrial circuits. When developing APWL-Y, we find out that 3-SMT wirelength is a power function of aspect ratio of bounding box of the given n-pin nets. The time complexity of APWL-Y is O(n). APWL-Y is very effective to guide the wirelength optimization in a HTP placer. Moreover, we develop an efficient HTP algorithm with wirelength optimization driven by APWL-Y estimator. The placement results by our placer subject to different optimization objectives are presented. Compared to the HTP placer with only area optimization, our placer can reduce the wirelength by 54.3% with a small area overhead of 9.07% on average. In addition, we explore the HPWL technique in the Y architecture. To the best of our knowledge, this paper is the first in-depth study on wirelength estimation technique in Y architecture and HTP floorplanning optimization with consideration of interconnects.