A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation

Authors:
Jing Li;Tan Yan;Bo Yang;Juebang Yu;Chunhui Li
Affiliations:
University of Electronic Science and Technology of China, Chengdu, China;University of Electronic Science and Technology of China, Chengdu, China;University of Electronic Science and Technology of China, Chengdu, China;University of Electronic Science and Technology of China, Chengdu, China;University of Electronic Science and Technology of China, Chengdu, China
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 6
Cited 1

An O-tree representation of non-slicing floorplan and its applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
The X architecture: not your father's diagonal wiring

SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A hierarchical three-way interconnect architecture for hexagonal processors

Proceedings of the 2003 international workshop on System-level interconnect prediction
Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
The Y-architecture: yet another on-chip interconnect solution

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

A non-Manhattan Hexagon/Triangle Placement (HTP for short) paradigm is proposed in the present paper. Main feature of this paradigm lies in adapting to the Y- architecture which is one of the promising non-Manhattan VLSI circuit layout architectures. Aim of the HTP is to place a set of equilateral triangles with given size onto a hexagonal chip with maximal chip area usage. Based on the O-tree representation, some adaptive packing rules are adopted to develop an effective placement algorithm for solving the HTP problem in BBL mode. Two examples with benchmark data transformed from the Manhattan BBL mode placement (ami33/49) are presented to justify the feasibility and effectiveness of our algorithms. Experiment results demonstrate that the chip area usage of 94% is achieved through simulated annealing optimization.