Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
VLSI theory and parallel supercomputing
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
HARTS: A Distributed Real-Time Architecture
Computer - Special issue on real-time systems
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Exploring Optimal Cost-Performance Designs for Raw Microprocessors
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
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The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wires are expensive. On the other hand, high performance systems require the shortest communication routes among the processors. Non-blocking hierarchical interconnect architectures have been found to be a feasible solution. First, they can be expanded recursively and so can be applied in large-scale arrays. Second, if well designed, they have the best trade-off between the cost of wire resources and the communication performance. In this paper, a new type of non-blocking hierarchical three-way interconnect architecture, Y tree architecture, is put forward. We find that the arrays of hexagonal cells also have the property of hierarchical expansion, and we put an algorithm to build up a Y tree. We compare the Y architecture with an X hierarchical non-blocking architecture.