A new polynomial-time algorithm for linear programming
Combinatorica
The maximum concurrent flow problem
Journal of the ACM (JACM)
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
Physical Planning Of On-Chip Interconnect Architectures
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
A hierarchical three-way interconnect architecture for hexagonal processors
Proceedings of the 2003 international workshop on System-level interconnect prediction
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 41st annual Design Automation Conference
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Rotationally optimal spanning and Steiner trees in uniform orientation metrics
Computational Geometry: Theory and Applications
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Diagonal routing in high performance microprocessor design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
Revisiting fidelity: a case of elmore-based Y-routing trees
Proceedings of the 2008 international workshop on System level interconnect prediction
Steiner trees for fixed orientation metrics
Journal of Global Optimization
Triplet-based topology for on-chip networks
WSEAS Transactions on Computers
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
Proceedings of the 11th international workshop on System level interconnect prediction
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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In this paper, we propose a new on-chip interconnect scheme called Y-architecture, which can utilize the on-chip routing resources more efficiently than traditional Manhattan interconnect architecture by allowing wires routed in three directions (0°, 60°, and 120°). To evaluate the efficiency of different interconnect architectures, we assume mesh structures with uniform communication demand and develop a multi-commodity flow (MCF) approach to model the on-chip communication traffic. We also extend the combinatorial MCF algorithm in [5] to compute the optimal routing resource allocations for different interconnect architectures. The experiments show that: (1) Compared with Manhattan architecture, the Y-architecture demonstrates a throughput improvement of 30.7% for square chip. The throughput of the Y-architecture is only 2.5% smaller than that of X-architecture. (2) A chip with the shape of a convex polygon produces better throughput than a rectangular chip: For Y-architecture, a hexagonal chip provides 41% more throughput than a squared chip using the Manhattan architecture. For Manhattan architecture, a diamond chip achieves a throughput improvement of 19.5% over the squared chip using the same interconnect architecture. (3) Compared with Manhattan architecture, the Y-architecture reduces the wire length of a randomly distributed two pin net by 13.4% and the average wire length of Y-architecture is only 4.3% more than that of the X-architecture.