Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Accuracy and fidelity of fast net length estimates
Integration, the VLSI Journal
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Steiner Minimal Tree Problem in the lambda-Geormetry Plane
ISAAC '96 Proceedings of the 7th International Symposium on Algorithms and Computation
Constructing exact octagonal steiner minimal trees
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spanning graph-based nonrectilinear steiner tree algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The dominance of interconnect delay in VLSI circuit design is well-known. Construction of routing trees in recent times has to take care of the timing issues for faster design convergence. Thus there is immense scope of research in design and performance of interconnects. Our current work encompasses two aspects of this research. On one hand, we consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilize this framework for verifying the supremacy of the Elmore delay estimate for its high fidelity. In order to ensure accurate computation of fidelity, (i) we propose new statistically proven formulae for fidelity, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of Elmore delay over that of linear delay.