Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions

Authors:
Parthasarathi Dasgupta
Affiliations:
Indian Institute of Management-Calcutta
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

Citing 0
Cited 2

Revisiting fidelity: a case of elmore-based Y-routing trees

Proceedings of the 2008 international workshop on System level interconnect prediction
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Deep sub-micron technology has increased the design complexity of VLSI circuits. Design of routers now has to take care of the timing issues for faster design convergence. This has yielded wider scope of research in design and performance of interconnects. We focus on certain critical aspects of interconnects, and related open research issues. The discussions are on (i) the fidelity of delay estimators, and its use in finding global routing trees, (ii) a new class of routing trees, and (iii) the evolution of new metric for interconnect performance measurement.