The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand for communication. A multi-commodity flow (MCF) model is proposed to find the throughput for several different routing architectures. The experimental results reveal several trends: 1. The throughput is limited by the capacity of the middle row and column in the mesh, simply enlarging the congested channel cannot produce better throughput. A flexible chip shape provides around 30% throughput improvement over a square chip of equal area. 2. A 45-degree mesh allows 17% throughput improvement over 90-degree mesh and a 90-degreeand 45-degree mixed mesh provides 30% throughput improvement. 3. To achieve maximum throughput on a mixed Manhattan and diagonal interconnect architecture, the best ratio of the capacity for diagonal routing layers and the capacity for Manhattan routing layers is 5.6. 4.Incorporating a simplified via model, interleaving diagonal routing layers and Manhattan routing layer is the best way to organize the wiring directions on different layers.