Hexagonal three-layer channel routing
Information Processing Letters
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 41st annual Design Automation Conference
Efficient octilinear Steiner tree construction based on spanning graphs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
X-Routing using Two Manhattan Route Instances
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Diagonal routing in high performance microprocessor design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the interconnect problem by reducing wire lengths directly. We present a non-Manhattan Steiner tree heuristic, obtaining wire length reductions of much as 17% on average, when compared to rectilinear topologies. Moreover, we present a graph-based interconnect optimization algorithm, called the GRATS-tree algorithm, which allows performance optimization beyond what can be obtained through wire length reduction alone. The two tree construction algorithms are integrated into a new global router that allows large scale non-Manhattan design. Although we consider circuit placements performed under rectilinear objectives, our global router can reduce maximum congestion levels by as much as 20%. In general we find that the non-Manhattan approach requires additional Steiner points and bends; realization of non-Manhattan routing structures requires additional vias. We observe that the increase in via cost is much less dramatic than might be expected; the benefits of wire length reduction may outweigh the additional via cost.