High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Creating and exploiting flexibility in steiner trees
Proceedings of the 38th annual Design Automation Conference
Improved approximations for shallow-light spanning trees
FOCS '97 Proceedings of the 38th Annual Symposium on Foundations of Computer Science
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven Steiner trees are (practically) free
Proceedings of the 43rd annual Design Automation Conference
Flexibility of steiner trees in uniform orientation metrics
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
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The rectilinear Steiner tree problem in the plane is to construct a minimum-length tree interconnecting a set of points (called terminals) consisting of horizontal and vertical line segments only. Rectilinear Steiner minimum trees (RSMTs) can today be computed quickly for realistic instances occurring in VLSI design. However, interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding an RSMT that -- as a secondary objective -- minimizes a signal delay related objective. Given a source (one of the terminals) we give some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present exact and heuristic algorithms for constructing RSMTs with weighted sum of path lengths or Elmore delays secondary objectives. Computational results for industrial designs are presented.