A fast and simple Steiner routing heuristic
Discrete Applied Mathematics - Special volume on VLSI
Balancing minimum spanning and shortest path trees
SODA '93 Proceedings of the fourth annual ACM-SIAM Symposium on Discrete algorithms
Approximating shallow-light trees
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Bicriteria Network Design Problems
ICALP '95 Proceedings of the 22nd International Colloquium on Automata, Languages and Programming
Improved approximations for shallow-light spanning trees
FOCS '97 Proceedings of the 38th Annual Symposium on Foundations of Computer Science
Delay-related secondary objectives for rectilinear Steiner minimum trees
Discrete Applied Mathematics - The 1st cologne-twente workshop on graphs and combinatorial optimization (CTW 2001)
SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closing the gap: near-optimal Steiner trees in polynomial time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 international symposium on Physical design
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Proceedings of the 46th Annual Design Automation Conference
Maze routing Steiner trees with delay versus wire length tradeoff
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
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Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimizes wirelength, an RSMT may take a "non-direct" route to a sink, which may give the designer an unnecessarily pessimistic view of the delay to the sink.Previous works have addressed this issue through performance-driven constructions, minimum Steiner arborescence, and critical sink based Steiner constructions. Physical synthesis and routing flows have been reticent to adapt universal timing-driven Steiner constructions out of fear that they are too expensive (in terms of routing resource and capacitance). This paper studies several different performance-driven Steiner tree constructions in order to show which ones have superior performance.A key result is that they add at most 2%-4% extra capacitance, and are thus a promising avenue for today's increasingly aggressive performance-driven P&R flows.We demonstrate using a production P&R flow that timing-driven Steiner topologies can be easily embedded into an incremental routing subflow to obtain significantly improved timing (3.6% and 5.1% improvements in cycle time for two industry testcases) at practically no cost of wirelength or routability.