Rectilinear shortest paths through polygonal obstacles in O(n(logn)2) time
SCG '87 Proceedings of the third annual symposium on Computational geometry
A faster approximation algorithm for the Steiner problem in graphs
Information Processing Letters
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane
Proceedings of the 2006 international symposium on Physical design
Timing-driven Steiner trees are (practically) free
Proceedings of the 43rd annual Design Automation Conference
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2008 international symposium on Physical design
Obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High-performance obstacle-avoiding rectilinear steiner tree construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The repeater tree construction problem
Information Processing Letters
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles
Proceedings of the International Conference on Computer-Aided Design
Shallow-Light steiner arborescences with vertex delays
IPCO'13 Proceedings of the 16th international conference on Integer Programming and Combinatorial Optimization
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We study the minimum rectilinear Steiner tree problem in the presence of obstacles. Traversing obstacles is not strictly forbidden, but the total length of each connected component in the intersection of the tree with the interior of the blocked area is bounded by a constant. This problem is motivated by the layout of repeater tree topologies, a central task in chip design. Large blockages might be crossed by wires on higher layers, but repeaters may not be placed within the blocked area. A too long unbuffered piece of interconnect would lead to timing violations. We present a 2-approximation algorithm with a worst case running time of O(k log k)^2, where k is the number of terminals plus the number of obstacle corner points. Under mild assumptions on the obstacle structure, as they are prevalent in chip design, the running time is O(k log k)^2. Compared to strictly obstacle-avoiding trees, the algorithm provides significantly shorter solutions. It solves real world instances with 783\,352 terminals within 126 seconds, proving its practical applicability.