The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Fast buffering for optimizing worst slack and resource consumption in repeater trees
Proceedings of the 2009 international symposium on Physical design
Binary trees with choosable edge lengths
Information Processing Letters
Shallow-Light steiner arborescences with vertex delays
IPCO'13 Proceedings of the 16th international conference on Integer Programming and Combinatorial Optimization
Discrete Applied Mathematics
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
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A tree-like substructure on a computer chip whose task is to carry a signal from a source circuit to possibly many sink circuits and which consists only of wires and so-called repeater circuits is called a repeater tree. We present a mathematical formulation of the optimization problems related to the construction of such repeater trees. Furthermore, we prove theoretical properties of a simple iterative procedure for these problems which was successfully applied in practice.