Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Spanning trees in hypergraphs with applications to steiner trees
Spanning trees in hypergraphs with applications to steiner trees
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Proceedings of the 46th Annual Design Automation Conference
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles
Proceedings of the 48th Design Automation Conference
Obstacle-avoiding rectilinear Steiner minimum tree construction: an optimal approach
Proceedings of the International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
Proceedings of the 2014 on International symposium on physical design
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This work studies the problem of finding a rectilinear Steiner minimum tree (RSMT) for a set of given terminals in the presence of obstacles. In modern VLSI designs, obstacles usually block the device layer and a fraction of metal layers. Therefore, routing wires on top of obstacles is possible. However, if a long wire is routed over an obstacle, there will be signal integrity problems because buffers cannot be placed on top of any obstacle. To tackle this problem, we impose slew constraints on the interconnects that are routed over an obstacle. This is called the obstacle-avoiding rectilinear Steiner minimum trees (OARSMT) problem with slew constraints over obstacles. In this paper, we first analyze an optimal solution to this problem and show that the tree structures over obstacles with slew constraints will follow some very simple forms. Based on this observation, we propose an algorithm to find an optimal solution embedded in the extended Hanan grid [1]. The solutions can guarantee the interconnect performance and avoid post-routing electrical fixups due to slew violations. We also show that our algorithm achieves over 800 times speedup and is able reduce nearly 5% routing resources on average in comparison with the state-of-the-art optimal OARSMT algorithm.