Power/ground networks in VLSI: are general graphs better than trees?
Integration, the VLSI Journal
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal planning for mesh-based power distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
Electromigration and voltage drop aware power grid optimization for power gated ICs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Analysis and optimization of power-gated ICs with multiple power gating configurations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Vertical via design techniques for multi-layered P/G networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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We consider the problem of determining optimal wire widths for a power or ground network, subject to limits on wire widths, voltage drops, total wire area, current density, and power dissipation. To account for the variation of the current demand, we model it as a random vector with known statistics, possibly including correlation between subsystem currents. Other researchers have shown that when the variation in the current is not taken into account, the optimal network topology is a tree. A tree topology is, however, almost never used in practice, because it is not robust with respect to variations in the lock currents. We show that when the current variation is taken into account, the optimal network is usually not a tree.We formulate a heuristic method based on minimizing a linear combination of total average power and total wire area. We show that this results in designs that obey the reliability constraints, occupy small area, and most importantly are robust against variations in block currents. The problem can be formulated as a nonlinear convex optimization problem that can be globally solved very effciently.