Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Optimal planning for mesh-based power distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An introduction to OpenAccess: an open source data model and API for IC design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
k-means++: the advantages of careful seeding
SODA '07 Proceedings of the eighteenth annual ACM-SIAM symposium on Discrete algorithms
2011 TAU power grid simulation contest: benchmark suite and results
Proceedings of the International Conference on Computer-Aided Design
PowerRush: a linear simulator for power grid
Proceedings of the International Conference on Computer-Aided Design
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
On the preconditioner of conjugate gradient method: a power grid simulation perspective
Proceedings of the International Conference on Computer-Aided Design
Least squares quantization in PCM
IEEE Transactions on Information Theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix Gs which is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%-32% reduction in power network area, compared with the results from modern commercial PG synthesizer.