DAC '96 Proceedings of the 33rd annual Design Automation Conference
Bounds on net lengths for high-speed PCB
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A multigrid tutorial: second edition
A multigrid tutorial: second edition
An exact algorithm for coupling-free routing
Proceedings of the 2001 international symposium on Physical design
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
Scaling trends of on-chip Power distribution noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
A System-Level Solution to Domino Synthesis with 2 GHz Application
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing with crosstalk constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing- and crosstalk-driven area routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On integrating power and signal routing for shield count minimization in congested regions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
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Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-micron designs. In this paper, we present a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints. The key part to this approach is a simple yet accurate power net estimation formula that decides the minimum number of power nets needed to satisfy both power and signal integrity constraints prior to detailed layout. The proposed design methodology is a one-pass solution to the co-design of power and signal networks in the sense that no iteration between them is required in order to meet design closure. Experiment results using large industrial benchmarks show that compared to the state-of-the-art alternative design approach, the proposed method can reduce the power network area by 19.4% on average under the same signal and power integrity constraints with better routing quality, yet use less runtime.