Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Towards global routing with RLC crosstalk constraints
Proceedings of the 39th annual Design Automation Conference
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect Geometry Optimization Using Modular Artificial Neural Networks
Analog Integrated Circuits and Signal Processing
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Adaptive Interconnect-Length Driven Placer
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layer assignment for crosstalk risk minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Shielding area optimization under the solution of interconnect crosstalk
Journal of Computer Science and Technology
Crosstalk-aware routing resource assignment
Journal of Computer Science and Technology
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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For the generation of a risk-free layout solution of a chip, crosstalk synthesis should be pursued at various stages in the routing process. This paper proposes a post global routing crosstalk optimization approach, which to our knowledge, is the first to estimate and reduce crosstalk risk at the global routing level. It consists of two parts: region-based crosstalk risk estimation and crosstalk risk reduction at the global routing level. In the first part, crosstalk risk graphs are first introduced for each routing region representing its current crosstalk situation. The crosstalk risk of each region, which indicates whether a risk-free routing solution of the region is possible, is then quantitatively defined and estimated using a graph-based approach. In the second part, the risk tolerance bound of each net is partitioned appropriately among its routing regions via integer linear programming for accurate (minimized) crosstalk risk estimation. If high risk regions still exist after bound partitioning, net ripping-up and rerouting is applied to reduce their crosstalk risks. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the current crosstalk situation of the chip. These can greatly facilitate the generation of a risk-free final solution at later stages in the layout process. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising