Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous signal and power routing under K model
Proceedings of the 2001 international workshop on System-level interconnect prediction
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Towards global routing with RLC crosstalk constraints
Proceedings of the 39th annual Design Automation Conference
Inductance Modeling for On-Chip Interconnects
Analog Integrated Circuits and Signal Processing
Post global routing RLC crosstalk budgeting
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Layout techniques for on-chip interconnect inductance reduction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analog Integrated Circuits and Signal Processing
Routing of analog busses with parasitic symmetry
Proceedings of the 2005 international symposium on Physical design
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
A new twisted differential line structure in global bus design
Proceedings of the 44th annual Design Automation Conference
Optimal positions of twists in global on-chip differential interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing signal timing variations in inter-core busses
Integration, the VLSI Journal
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. The effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16-bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation.