Layout techniques for on-chip interconnect inductance reduction

Authors:
Shang-Wei Tu;Jing-Yang Jou;Yao-Wen Chang
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;National Taiwan University, Taipei, Taiwan, R.O.C.
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 4
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Abstract

As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques -- ground-aware net routing and source pin positioning - that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry [7] to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.