Inductance Modeling for On-Chip Interconnects

Authors:
Shang-Wei Tu;Wen-Zen Shen;Yao-Wen Chang;Tai-Chen Chen;Jing-Yang Jou
Affiliations:
Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan ROC kuma@athena.ee.nctu.edu.tw;Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan ROC wzshen@cc.nctu.edu.tw;Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan ROC ywchang@cc.ee.ntu.edu.tw;Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan ROC tcchen@eda.ee.ntu.edu.tw;Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan ROC jyjou@bestmap.ee.nctu.edu.tw
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2003

Citing 7
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Abstract

As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.