Reliability analysis and optimization of power-gated ICs

Authors:
Aida Todri;Malgorzata Marek-Sadowska
Affiliations:
Fermi National Accelerator Laboratory, Batavia, IL;Electrical and Computer Engineering Department, University of California, Santa Barbara, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

Citing 13
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Abstract

Power gating is an efficient technique for reducing the leakage power of electronic devices by disconnecting the power supply from blocks idle for long periods of time. Disconnecting gated blocks causes changes in the current densities of the grid branches and vias. For some gating configurations, dc current densities may increase in some grid locations to the extent that they violate electromigration (EM) constraints. In this paper, we analyze the EM and infrared (IR) voltage drop effects in gated global power grids. Based on our analyses, we develop a global grid sizing algorithm to satisfy the reliability constraints on grid branches and vias for all feasible gating configurations. Our experimental results indicate that a grid initially sized for all blocks connected to it may be modified to fulfill EM and IR constraints for multiple gating schedules with only a small area increase.