A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
An effective gated clock tree design based on activity and register aware placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Post-Placement Power Optimization With Multi-Bit Flip-Flops
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISPD11: Power-Driven Flip-Flop Merging and Relocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.