Novel pulsed-latch replacement based on time borrowing and spiral clustering

Authors:
Chih-Long Chang;Iris H.-R. Jiang;Yu-Ming Yang;Evan Y.-W. Tsai;Aki S.-H. Chen
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan Roc;National Chiao Tung University, Hsinchu, Taiwan Roc;National Chiao Tung University, Hsinchu, Taiwan Roc;Faraday Technology Corp., Hsinchu, Taiwan Roc;Faraday Technology Corp., Hsinchu, Taiwan Roc
Venue:
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Year:
2012

Citing 13
Cited 2

An efficent clustering algorithm for low power clock tree synthesis

Proceedings of the 2007 international symposium on Physical design
A robust, fast pulsed flip-flop design

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Resurrecting infeasible clock-gating functions

Proceedings of the 46th Annual Design Automation Conference
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits

Proceedings of the 2009 International Conference on Computer-Aided Design
Pulsed-latch aware placement for timing-integrity optimization

Proceedings of the 47th Design Automation Conference
Statistical time borrowing for pulsed-latch circuit designs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An effective gated clock tree design based on activity and register aware placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pulser gating: a clock gating of pulsed-latch circuits

Proceedings of the 16th Asia and South Pacific Design Automation Conference
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs

Proceedings of the 2011 international symposium on Physical design
Pulsed-latch-based clock tree migration for dynamic power reduction

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs

Proceedings of the International Conference on Computer-Aided Design
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

Proceedings of the International Conference on Computer-Aided Design

Placement: hot or not?

Proceedings of the International Conference on Computer-Aided Design
Power optimization for clock network with clock gate cloning and flip-flop merging

Proceedings of the 2014 on International symposium on physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed-latches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.