Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-Power CMOS Design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Pulsed-latch-based clock tree migration for dynamic power reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip-flops. In this paper, we present a pulsed flip-flop design based on a novel pulse generator circuit. Our design achieves significantly improved speed when compared to recent pulsed flip-flop design, as well as a traditional master-slave D flip-flop. Monte Carlo simulations demonstrate that our design is significantly more robust to variations than the other flip-flops. Our design consumes low power as well. Also we have performed the layout of our design and shown that our layout area is smaller than a traditional D flip-flop.