A sweepline algorithm for Voronoi diagrams
SCG '86 Proceedings of the second annual symposium on Computational geometry
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
A robust, fast pulsed flip-flop design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Statistical time borrowing for pulsed-latch circuit designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pulser gating: a clock gating of pulsed-latch circuits
Proceedings of the 16th Asia and South Pacific Design Automation Conference
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Proceedings of the International Conference on Computer-Aided Design
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hi-index | 0.00 |
Minimizing the clock tree has been known as an effective approach to reduce power dissipation in modern circuit designs. However, most existing power-aware clock tree synthesis algorithms still focus on optimizing power in flip-flops, which might have limited power savings. In this work, we explore the pulsed-latch utilization in clock tree synthesis for further power savings. We are the first work in the literature to propose a novel synthesis algorithm to efficiently migrate a flip-flop-based clock tree into a pulsed-latch one. To maintain performance of a clock tree while considering load balance (skew issues) simultaneously, we determine the clock tree topology by the minimum-cost maximum-flow network. Experimental results show that our algorithm can further reduce power consumption by 22% on average compared to approaches without pulsed latches.