Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Constrained clock shifting for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Statistical time borrowing for pulsed-latch circuit designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pulsed-latch-based clock tree migration for dynamic power reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Proceedings of the International Conference on Computer-Aided Design
Useful-skew clock optimization for multi-power mode designs
Proceedings of the International Conference on Computer-Aided Design
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Pulsed latches, latches driven by a brief clock pulse, offer the convenience of flip-flop-like timing verification and optimization, while retaining superior design parameters of latches over flip-flops. But, pulsed latch-based design using a single pulse width has a limitation in reducing clock period. The limitation still exists even if clock skew scheduling is employed, since the amount of skew that can be assigned is practically limited due to process variations. The problem of allocating pulse width (out of discrete number of predefined widths) and scheduling clock skew (within prescribed upper bound) is formulated, for the first time, for optimizing pulsed latch-based sequential circuits. An allocation algorithm called PWCS_Optimize is proposed to solve the problem. Experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum clock period for many benchmark circuits. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.