A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
Activity and register placement aware gated clock network design
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Pulsed-latch-based clock tree migration for dynamic power reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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Pulsed latches have emerged as a popular technique to reduce the power consumption and delay for clock networks. However, the current physical synthesis flow for pulsed latches still performs circuit placement and clock-network synthesis separately, which limits achievable power reduction. This paper presents the first work in the literature to perform placement and clock-network co-synthesis for pulsed-latch designs. With the interplay between placement and clock-network synthesis, the clock-network power and timing can be optimized simultaneously. Novel progressive network forces are introduced to globally guide the placer for iterative improvements, while the clock-network synthesizer makes use of updated latch locations to optimize power and timing locally. Experimental results show that our framework can substantially minimize power consumption and improve timing slacks, compared to existing synthesis flows.