Activity-sensitive clock tree construction for low power
Proceedings of the 2002 international symposium on Low power electronics and design
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
An effective gated clock tree design based on activity and register aware placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Proceedings of the International Conference on Computer-Aided Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
The optimal fan-out of clock network for power minimization by adaptive gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wirelength overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous design flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted. In this work, we propose a new design flow for low power gated clock network construction, in order to minimize the clock wirelength and the activity of control signals, and to eliminate the overlaps incurred by the gate logics. Our method begins with a coarse placement followed by soft register clustering. Then, we perform clock tree topology construction and zero skew clock routing to further reduce the power and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware register placement in clock wirelength and clock power reduction with signal nets wirelength and signal nets power increase within 5% and 3%, respectively