Activity-sensitive clock tree construction for low power

Authors:
Chunhong Chen;Changjun Kang;Majid Sarrafzadeh
Affiliations:
University of Windsor, Windsor, Canada;University of Windsor, Windsor, Canada;University of California at Los Angeles, Los Angeles, CA
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 2
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Abstract

This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node difference between different modules to optimize the power consumption due to the interconnections (i.e., clock gating signals and clock edges). We also develop a method to determine gating signals with minimum number of transitions. After the clock tree is constructed, the gating signals are optimized for further power savings.