CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
On Boolean and Arithmetic Masking against Differential Power Analysis
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An Implementation of DES and AES, Secure against Some Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Proceedings of the 42nd annual Design Automation Conference
Investigations of power analysis attacks on smartcards
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A secure and low-energy logic style using charge recovery approach
Proceedings of the 13th international symposium on Low power electronics and design
Masking and Dual-Rail Logic Don't Add Up
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
A table masking countermeasure for low-energy secure embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
A digital design flow for secure integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic design flow for implementation of side channel attacks resistant crypto-chips
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This paper proposes a new ASIC design flow using latch retiming and random clock-gating to cope with power analysis side-channel attacks. We cast the side-channel attack problem as a combination of retiming and clock-gating problems and solve the problems using only existing EDA tool chains. In particular, we achieve light weight time-shifting obfuscation against DPA (Differential Power Analysis) and CPA (Correlation Power Analysis) attacks by changing when to latch randomly. Our proposed LRCG (Latch-based Random Clock-Gating) method incurs only 13% of hardware area overhead that is significantly smaller than other balancing and masking countermeasures which require 100% and 294% overhead, respectively. Our experimental results show that LRCG incurs only negligible performance and energy consumption penalty, while successfully preventing DPA and CPA attacks in all cases.