Introduction to algorithms
IEEE Transactions on Computers
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Constrained clock shifting for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Skew-programmable clock design for FPGA and skew-aware placement
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
In-Circuit Self-Tuning of Clock Latencies
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Delay insertion method in clock skew scheduling
Proceedings of the 2005 international symposium on Physical design
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Self-tuning adaptive delay sequential elements
Microelectronics Journal
Early planning for clock skew scheduling during register binding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A fast incremental clock skew scheduling algorithm for slack optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Dual-Vth leakage reduction with fast clock skew scheduling enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
A practical method for multi-domain clock skew optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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The application of general clock skew scheduling is practicallylimited due to the difficulties in implementing a wide spectrum ofdedicated clock delays in a reliable manner. This results in a significantlimitation of the optimization potential. As an alternative,the application of multiple clocking domains with dedicatedphase shifts that are implemented by reliable, possibly expensivedesign structures can overcome these limitations and substantiallyincrease the implementable optimization potential of clock adjustments.In this paper we present an algorithm for constrained clockskew scheduling which computes for a given number of clockingdomains the optimal phase shifts for the domains and the assignmentof the individual registers to the domains. For the within-domainlatency values, the algorithm can assume a zero-skew clockdelivery or apply a user-provided upper bound. Our experimentsdemonstrate that a constrained clock skew schedule using a fewclocking domains combined with small within-domain latency canreliably implement the full sequential optimization potential to dateonly possible with an unconstrained clock schedule.