IEEE Transactions on Computers
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Practical Fast Clock-Schedule Design Algorithms*The preliminary version was presented at [1].
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
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We propose a fast clock skew scheduling algorithm which minimizes clock period and enlarges the slacks of timing critical paths. To reduce the runtime of the timing analysis engine, our algorithm allows the sequential graph to be partly extracted. And the runtime of itself is almost linear to the size of the extracted sequential graph. Experimental results show its runtime is less than a minute for a design with more than ten thousands of flip-flops.