Practical Fast Clock-Schedule Design Algorithms*The preliminary version was presented at [1].

Authors:
Atsushi Takahashi
Affiliations:
The author is with the Graduate School of Science and Technology, Tokyo Institute of Technology, Tokyo, 152-8552 Japan. E-mail: atsushi@lab.ss.titech.ac.jp
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2006

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Abstract

In this paper, a practical clock-scheduling engine is introduced. The minimum feasible clock-period is obtained by using a modified Bellman-Ford shortest path algorithm. Then an optimum cost clock-schedule is obtained by using a bipartite matching algorithm. It also provides useful information to circuit synthesis tools. The experiment to a circuit with about 10000 registers and 100000 signal paths shows that a result is obtained within a few minutes. The computation time is almost linear to the circuit size in practice.