A fast clock scheduling for peak power reduction in LSI

Authors:
Yosuke Takahashi;Yukihide Kohira;Atsushi Takahashi
Affiliations:
Tokyo Institute of Technology, Tokyo, Japan;Tokyo Institute of Technology, Tokyo, Japan;Tokyo Institute of Technology, Tokyo, Japan
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

Citing 4
Cited 0

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Abstract

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast power estimation method for the clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed power estimation method, the proposed clock scheduling method finds clock schedules for benchmark circuits that greatly reduce the peak power in a few minutes.