IEEE Transactions on Computers
Practical Fast Clock-Schedule Design Algorithms*The preliminary version was presented at [1].
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
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A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and replaces intermediate registers with delay elements under the condition that the circuit works correctly at given target clock-period range with the smaller area. Experiments with pipelined multipliers verify that the proposed algorithm can reduce the area of a pipelined circuit without degrading performance.